The present invention relates to a semiconductor device having a highly reliable groove isolation structure and a process for producing the same.
A shallow groove isolation (SGI) structure is now available to make an electrical insulation or isolation between adjacent elements such as transistors, etc. on a semiconductor substrate. As shown in FIGS. 1A to 1D, the SGI structure typically comprises a shallow groove formed on a semiconductor substrate 31 of silicon and an oxide film 35 and the like embedded in the groove and is suitable for devices requiring processing dimensional precision of 0.25 xcexcm or under, because its processing dimensional precision is higher than that of the structure so far by local oxidation of silicon (LOCOS). However, the SGI structure sometimes suffers from formation of sharp protrusions 34 of semiconductor substrate 31 of silicon formed in the oxide film 35 formed by oxidation at the upper edge of the groove during the oxidation step, as shown in FIG. 1C. The presence of such sharp protrusions 34 of semiconductor substrate 31 of silicon causes concentration of electric fields around the protrusions during the circuit operation, sometimes deteriorating gate breakdown voltage or capacitance, as disclosed, for example, by A. Bryant et al (Technical Digest of IEDM ""94, pp. 671-674). It is known from experiences that such deterioration of gate breakdown voltage occurs when the radius of curvature of the substrate is not more than 3 nm around the groove upper edge, even if the angle of substrate is not less than 90xc2x0 around the groove upper edge. To overcome the deterioration, pad oxide film 32 of FIG. 1B is recessed backwards by about 0.1 xcexcm as shown in FIG. 1Bxe2x80x2 and oxidized with an oxidant, preferably steam at a temperature of about 1,000xc2x0 C. to form a desired radius of curvature at the groove upper edges, as disclosed in JP-A-2-260660.
Even though the desired radius curvature can be obtained by the prior art procedure, step (or unevenness) 44 is formed on the upper surface of semiconductor substrate of silicon 31 around the groove upper edge, as shown in FIG. 1Cxe2x80x2. Such step 44 can be formed presumably due to the following mechanism. That is, semiconductor substrate 31 of silicon has a silicon-exposed region and a silicon-unexposed region in the recessed area at the edge of pad oxide film 32; the silicon-exposed region undergoes faster oxidant diffusion, i.e. faster oxidation, than the silicon-unexposed region, resulting in formation of step 44 at the edge of pad oxide film 32 as a boundary. Gate oxide film 37, when formed in such a step region, has an uneven thickness, which leads to variations of electrical properties. Furthermore, stresses are liable to concentrate therein, resulting in a possible decrease in the electrical reliability of a transistors to be formed on step 44.
Further, the silicon oxide film 36 is deposited on the semiconductor substrate 31 by chemical vapor deposition (CVD) to embed the silicon oxide film 36 in the groove and then the semiconductor substrate 31 is heat treated to sinter the silicon oxide film 36 embedded in the groove. Sintering is carried out for improving the quality of the silicon oxide film 36 embedded in the groove. If the sintering is insufficient, voids are often generated in the groove in the subsequent steps.
Furthermore, it is said that wet or steam oxidation is effective for sintering the silicon oxide film 36 embedded in the groove, but the wet or steam oxidation is liable to oxidize the inside, particularly side wall, of the groove. Oxidation starts from the groove surface and thus the groove bottom is less oxidized. Once the groove side wall is oxidized, the active region is narrowed. This is another problem. Thicker oxide film will cause a larger stress on the boundary between the oxide film and the substrate and the once rounded shoulder edge will return to the original sharp one and crystal defects are also generated. This is a further problem. To overcome these problems, it was proposed to provide a silicon nitride film along the groove inside wall.
According to a process for forming a groove, disclosed in JP-A-8-97277, a groove is trenched on a silicon substrate at first, and then an oxide film is formed on the groove inside surfaces (side wall and bottom surfaces) by heat oxidation, followed by further formation of a silicon nitride film thereon and still further formation of a silicon film such as anyone of amorphous, polycrystalline and monocrystalline silicon films on the silicon nitride film. Then, the groove is embedded with a silicon oxide film completely, followed by flattening of the groove top. After the deposition of the silicon oxide film on the entire surface of substrate, but before the fattening, the silicon film is oxidized in an oxidizing atmosphere including steam at about 950xc2x0 C. to convert it to a silicon oxide film. The silicon substrate is not oxidized during the oxidation, because the silicon substrate is protected by the silicon nitride film. According to the process, a film having a good compatibility with a silicon oxide film, i.e. a silicon film is formed as a thin film on the groove inside surfaces and thus the groove can be embedded with the silicon oxide film without any remaining voids in the groove. The silicon film in the groove must be then converted to a silicon oxide film by oxidation, but the silicon nitride film is provided between the silicon film and the silicon substrate, the silicon substrate is never oxidized during the oxidation of the silicon film. That is, no device characteristics are deteriorated at all.
In the above-mentioned prior art processes for forming a groove, heat treatment is carried out at a high temperature such as 1,000xc2x0 C. or higher to round the shoulder edge of element isolation groove. However, large-dimension wafers are liable to undergo dislocation, which will serve as nuclei for defects, by heat treatment at a high temperature such as 1,000xc2x0 C. or higher, and thus a heat-treatment process at a high temperature such as 1,000xc2x0 C. or higher would be hard to use in view of the future trend to use much larger-dimension wafers. In the heat treatment at a low temperature such as less than 1,000xc2x0 C., it is hard to round the shoulder edge of element isolation groove.
An object of the present invention is to provide a semiconductor device with a desired radius of curvature formed at the groove upper end and without formation of any step there, and also a process for producing the same.
The object of the present invention can be attained by reducing the stress generation around the groove upper end of an element isolation groove on a semiconductor substrate.
Another object of the present invention is to provide a novel technique of optimizing the shape of an element isolation groove, thereby making the device finer and improving the device electric characteristics.
Other object of the present invention is to provide a novel technique of reducing an adverse effect of stresses to an active region due to the sintering of a silicon oxide film embedded (or buried) in an element isolation groove on the device characteristics.
The present invention provides a process for producing a semiconductor device, which comprises the following steps:
(1) a step of forming a pad oxide film having a thickness of at least 5 nm, preferably at least 10 nm on a circuit-forming side of a semiconductor substrate (or a silicon substrate),
(2) a step of forming an anti-oxidation film on the pad oxide film,
(3) a step of trenching a groove to a desired depth at a desired position on the circuit-forming side of the semiconductor substrate,
(4) a step of recessing the pad oxide film to an extent of 5 nm-40 nm from the inside wall of the groove,
(5) a step of oxidizing the inside wall of the groove trenched on the semiconductor surface,
(6) a step of embedding an isolation film in the oxidized groove,
(7) a step of removing the embedding isolation film formed on the anti-oxidation film,
(8) a step of removing the anti-oxidation film formed on the circuit-forming side of the semiconductor substrate, and
(9) a step of removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate.
The present invention further provides a semiconductor device which comprises a semiconductor (or silicon) substrate and an element isolation oxide film having a groove isolation structure formed on the circuit-forming side of the semiconductor substrate, where the substrate has a monotonously convexed shape around the upper edge of the groove of the groove isolation structure; the oxide film is oxidized to have a thickness of 5 to 70 nm, preferably 30 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure; and the semiconductor substrate has a radius of curvature in a range of 3 to 35 nm at the upper edge of the groove thereof.
The present invention further provides a process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor (or silicon) substrate, thereby forming a first silicon oxide film as a pad oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film as an anti-oxidation film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove within the range for filling the second silicon oxide film in the recess space formed up to the edge of the recessed first silicon oxide film and rounding the shoulder edge of the groove at the same time,
(d) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove,
(f) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and
(g) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove and then forming a semiconductor element in the active region.
The present invention further provides a process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film and the first silicon oxide film residing in an element isolation region while masking an element region,
(b) a step of isotropically and shallowly etching the surface of the semiconductor substrate in the element isolation region, thereby providing an undercut on the semiconductor substrate at the edge of the element isolation region,
(c) a step of selectively etching the semiconductor substrate in the element isolation region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate,
(d) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time,
(e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(f) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove,
(g) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and
(h) a step of removing the silicon nitride film on the surface of an active region whose circumference is confined by the element isolation groove and then forming a semiconductor element in the active region.
The present invention further provides numbers of variations of the above-mentioned processes.